1. Field of the Invention
The present invention relates to digital modulators and digital demodulators with quadrature amplitude modulation (QAM) schemes, and more specifically, to a digital modulator and a digital demodulator used in multiplexed channel radio communications equipment, cable television (CATV) systems, and the like.
2. Description of the Related Art
The use of digital signal processing technologies has become dominant in actual implementation of modulators and demodulators with quadrature amplitude modulation (QAM) schemes. It is because the digital technologies, when compared to analog technologies, provide better accuracy and enable easier integration of QAM functionalities into an LSI chip. However, as the number of data bits for each symbol is increased, it becomes necessary to expand the scale of digital circuits of a modulator or demodulator in order to process an increased amount of data, thus causing some problems in costs and power consumption of the circuits. To solve such problems, designers have been urged to devise some methods of reducing the scale of digital modulator and demodulator circuits. In such a circumstance, the present invention provide solutions for the increasing demands.
The following items (i) to (v) will explain some specific configurations of conventional QAM modulators and demodulators, for basic understanding of backgrounds of their potential problems.
(i) FIG. 18 is a block diagram showing a conventional digital modulator. Two baseband signals of an in-phase channel (I-ch) and a quadrature channel (Q-ch) are supplied to their respective roll-off filters 101 and 102 for rejecting off-range frequency signals to minimize the intersymbol interference. The two roll-off filters 101 and 102 have identical internal structure as shown in FIG. 19.
Referring to FIG. 19, flip-flops 103a, 103b, 103c, and so on are connected in series, each of which actually carries a multiple-bit value representing each instant amplitude of a baseband signal. Being triggered at intervals of T/4, those flip-flops successively provide the entered baseband signals with T/4 delays, where T is the cycle period of a carrier clock signal. The delayed baseband signals are then supplied to their respective multipliers 104a, 104b, 104c, and so on, which separately multiply the signals by predetermined tap coefficients xcex1n, xcex1nxe2x88x921, xcex1nxe2x88x922, and so on at T/4 intervals. An adder 105 then collects the resultant products for calculating their summation at every T/4 period. The tap coefficients are designed to yield a desired impulse response, and the different values are symmetrically arranged along that multiplier array as shown in FIG. 19, with a coefficient xcex10 placed at the central tap.
Returning to FIG. 18, the outputs of the roll-off filters 101 and 102 are provided to multipliers 106 and 107 for simultaneous multiplication by two orthogonal carrier signals, cos xcfx89t and sin xcfx89t, respectively. The multiplier 106 multiplies the output of the roll-off filter 101 by a carrier signal cos xcfx89t at T/4 intervals, while the other multiplier 107 multiplies the output of the other roll-off filter 102 by another carrier signal sin xcfx89t at the same intervals. An adder 108 calculates a sum of their products at T/4 intervals, thus obtaining a modulated signal in the form of a sequence of digital values. A digital-to-analog (D/A) converter 109 converts this modulated signal into an analog signal also at T/4 intervals. A low-pass filter 110 eliminates alias components, or undesired harmonic frequencies, included in the output of the D/A converter 109.
Assume here that the frequency f of the carrier signals cos xcfx89t and sin xcfx89t is equal to the symbol rate. Since the multipliers 106 and 107 operate at intervals of T/4 as described before, the actual waveforms of the carrier signals, cos xcfx89t and sin xcfx89t, applied to them can be expressed as:
cos xcfx89t=[1, 0, xe2x88x921, 0, . . . ]xe2x80x83xe2x80x83(1a)
sin xcfx89t=[0, 1, 0, . . . ]xe2x80x83xe2x80x83(1b)
Let the output signal sequence of the roll-off filter 101 be [I1, I2, I3, I4, . . . ], and that of the roll-off filter 102 be [Q1, Q2, Q3, Q4, . . . ]. Based on the values shown in the expressions (1a) and (1b), the modulated signal entered to the D/A converter 109 will be expressed as [I1, Q2, xe2x88x92I3, xe2x88x92Q4, . . . ].
The result of the above discussion allows such an alternate circuit configuration as illustrated in FIG. 20, where the multipliers 106 and 107 and adder 108 in FIG. 18 are replaced with a combination of inverters 115 and 116 and a parallel-to-serial (P/S) converter 117.
In a digital modulator circuit of FIG. 20, the I-ch baseband signal is supplied to two roll-off filters 111 and 112 and the Q-ch baseband signal is entered to two roll-off filters 113 and 114. These four roll-off filters 111-114, having the same internal structure as shown in FIG. 19, operate at a rate of four times as high as the carrier frequency (or the symbol rate, in this case). The P/S converter 117 has four input terminals A, B, C, and D. The inputs A and B are connected directly to the output of the roll-off filters 111 and 113, respectively. On the other hand, the inputs C and D receive inverted signals of the outputs of the roll-off filters 112 and 114 via inverters 115 and 116, respectively. At the rate of four times the carrier frequency, the P/S converter 117 sequentially and cyclically selects one of those inputs from A toward D and feeds the selected signal to the D/A converter 109.
Such an alternate circuit configuration as shown in FIG. 20 is disclosed in Japanese Patent Laid-open Publications No. 3-265332 (1991) and No. 6-104943 (1994), for example.
(ii) Carrier frequency used in a digital modulator is normally selected to be an integral multiple of its symbol rate, namely, n times the symbol rate. As clarified in FIG. 18, a digitally modulated signal is converted to an analog signal by the D/A converter 109 at T/4 intervals. This D/A conversion process will cause some alias frequency components imposed in the spectrum of the resultant analog signal, of which central frequencies derive from the cycle time of the D/A conversion. The alias can be filtered out by using the low-pass filter 110. As the carrier frequency is lowered, the cutoff frequency of the low-pass filter 110 should also be reduced. Because low-pass filters with low cutoff frequencies are costly in general, a higher carrier frequency is desirable for cost reduction of modulator devices. Therefore, when the ratio of carrier frequency to symbol rate is n:1 (n is an integer), it is desired to set this factor n as high as possible.
(iii) FIG. 21 is a block diagram showing a combination of a conventional digital modulator and demodulator. The modulator shown on the left hand of FIG. 21 has basically the same structure as that in FIG. 18, while FIG. 21 includes some more details. The following description will focus on its distinctive points, maintaining consistent reference numerals for the common elements.
In FIG. 21, a carrier clock signal having a frequency  (i.e., n times the symbol rate) is produced by a carrier frequency oscillator 120. A splitter 121 then divides it into two ways and delivers one as is to the multiplier 106, as well as supplying the other to the multiplier 107 with a phase shift of 90 degrees. Another oscillator 122 generates a signal having a frequency equal to difference between a radio frequency  and the carrier frequency . This  signal is provided to a frequency converter 123 for upconversion of the low-pass filter output. That is, while the frequency content of a modulated signal produced by the low-pass filter 110 is centered around the carrier frequency , the frequency converter 123 shifts it upward to higher radio frequencies by using the  signal, thereby outputting to a transmission line a modulated radio signal whose spectral density is centered around the radio frequency .
On the other hand, a digital demodulator shown in the right half of FIG. 21 reproduces the I-ch and Q-ch signals from the received radio signal through a demodulation process, which applies exactly the same operators as those in the modulation process but in inverse order.
(iv) FIG. 22(A) is a block diagram of a conventional digital demodulator, and FIG. 22(B) illustrates the internal structure of a signal level detector 132 as part of the demodulator in FIG. 22(A).
The reception signal is first sent to an automatic gain control (AGC) circuit 130 for regulating its signal strength to a constant level according to a control signal from the signal level detector 132. An analog-to-digital (A/D) converter 131, coupled to the AGC circuit 130, performs a signal conversion from an analog voltage to a digital value and sends it to a demodulator section 133 and also to the signal level detector 132. The signal level detector 132 detects an average signal level by observing the digital reception signal sent from the A/D converter 131. If the average signal level does not agree with a predetermined level, the signal level detector 132 sends a control signal to the AGC circuit 130, thus regulating the reception signal level.
The details of the signal level detector 132 are shown in FIG. 22(B). An absolute value detector 135 calculates an absolute value of the digital reception signal provided from the A/D converter 131. A subtractor 136 further calculates the difference between the absolute value and a preprogrammed value. The differences are integrated in the time domain by an integrator composed of an adder 137 and a flip-flop 138. The result of this time-integration is converted to an analog signal by a D/A converter 139, for use as the control voltage for the AGC circuit 130.
(v) In the conventional digital modulator shown in FIG. 18, a D/A conversion performed by the D/A converter 109 will cause some distortion in the frequency content of the converted signal. Generally, the frequency response of a D/A converter is expressed as
|sin(xcfx89/2S)|/(xcfx89/2S)xe2x80x83xe2x80x83(2)
where S is a sampling rate. This Equation (2) implies that the output of a D/A converter loses its gain in a high frequency range, or the first-order attenuation.
The above explanations gave some specific configurations of conventional QAM modulators and demodulators. The following part will now clarify their potential problems, recalling each of the above-described points (i) to (v),
(i) In the conventional digital modulator shown in FIG. 20, it is difficult to increase the number of bits per symbol, because its roll-off filters are too large in circuit scale. Since the number of multipliers integrated therein and the data length of each multiplier are particularly critical to the scale of roll-off filters, it is necessary to reduce the number of multipliers. Also, the roll-off filters in this conventional modulator should operate at a frequency of four times the carrier frequency. Therefore, raising the carrier frequency will result in larger electric power consumed in the roll-off filters.
As such, the reduction of circuit scale and power consumption in roll-off filters are the crucial demands for further enhancement of the conventional digital modulator in FIG. 20.
(ii) Recall that a higher ratio of the carrier frequency to the symbol rate is desirable for cost reduction of modulator devices. This requirement for a higher carrier frequency, however, will naturally cause an increase of the circuit scale since such digital modulators must operate four times as fast as that higher carrier frequency.
(iii) The conventional digital modulator shown in FIG. 21 is equipped with the oscillator 122 to obtain a frequency equal to the difference between radio frequency  and carrier frequency . Such a  oscillator is also required in digital demodulator. However, there is such a problem with those oscillators that their oscillation frequency has to be changed when a different carrier frequency  is requested. In addition, since the carrier frequency is set to an integer multiple (i.e., n times) of the symbol rate, it is necessary to modify the oscillator 122 and its counterpart in the demodulator, when a different multiplication ratio n is required.
(iv) In the conventional digital demodulator shown in FIG. 22, the A/D converter 131 and signal level detector 132 operate at the carrier frequency. Therefore, these devices must work faster to obtain a higher ratio of the carrier frequency to the symbol rate, thus causing an increase in their costs.
(v) Further, in any of the foregoing prior-art digital modulators, a digital-to-analog conversion applied to a modulated signal by a D/A converter will cause a reduction of the high frequency range gain. However, from the viewpoint of compliance with legal regulations on radio wave emission and/or noise immunity, it is desired to keep a flat frequency response.
Taking the above into consideration, a first object of the present invention is to provide a digital modulator which enables downsizing of roll-off filter circuits and reduction of their power consumption.
A second object of the present invention is to provide a digital modulator whose circuit size is not increased even when a higher value is selected for the ratio of carrier frequency to symbol rate.
A third object of the present invention is to provide a digital modulator and a digital demodulator in which a local oscillator for frequency conversion can be used without modification even if the carrier frequency is required to change.
A fourth object of the present invention is to provide a digital demodulator which avoids cost increase in an AGC circuit, even when a higher ratio of carrier frequency to symbol rate is selected.
A fifth object of the present invention is to provide a digital modulator in which the modulated signal converted by a D/A converter is compensated to obtain a flat frequency response.
To accomplish the above objects, according to the present invention, there is provided a digital modulator with a quadrature amplitude modulation scheme. The digital modulator comprises a first and a second roll-off filters for transmitting a desired frequency range of a return-to-zero coded I-channel baseband signal, a third and a fourth roll-off filters for transmitting a desired frequency range of a return-to-zero coded Q-channel baseband signal. The modulator also comprises first and second inverting means for inverting the outputs of the second roll-off filter and fourth roll-off filter, respectively. The above six structural elements all operate at a first predetermined clock frequency. The modulator further comprises selection means and D/A conversion means operating at a second predetermined clock frequency that is four times as high as the first predetermined clock frequency. The selection means successively selects one of a first to fourth input signals, where the first to fourth input signals are the respective outputs of the first roll-off filter, the third roll-off filter, the first inverting means, and the second inverting means. The D/A conversion means converts the output of the selection means into an analog signal.
To accomplish the above objects, there is also provided a digital demodulator having a demodulation circuit with a quadrature amplitude modulation scheme. The digital demodulator comprises carrier signal supplying means for supplying the demodulation circuit with a carrier signal having a carrier frequency derived from a symbol rate, and radio frequency generation means for generating a radio frequency signal having a predetermined radio frequency. The demodulator further comprises difference frequency generation means and downconversion means. The difference frequency generation means generates a difference frequency signal by using the carrier signal produced by the carrier signal supplying means and the radio frequency signal generated by the radio frequency generation means. The difference frequency signal has a frequency equal to the difference between the predetermined radio frequency and the carrier frequency. The downconversion means converts a frequency of a radio input signal down to the carrier frequency by using the difference frequency signal generated by the difference frequency generation means.